With each new generation of integrated circuit (IC) development, more and more functionality is being integrated into a single IC. In general, integration leads to smaller ICs, better performance, and lower production costs. However, a reduction in IC size and production cost is often limited by the lack of cost effective IC packaging techniques. As a result, designers are always looking for ways to minimize the number of IC pins associated with a given device. A reduction in the number of IC package pins may be effected by 1) limiting functionality, or 2) sharing functionality.
For example, a simplified Pentium.RTM. or Pentium-Pro.RTM. computer system 900, 1000 (FIGS. 9 & 10) might comprise a central processing unit (CPU) 902, 1004, a main memory 910, 1008, and a second level cache memory (L2 cache) 904, 1002. The CPU 902, 1004 comprises a single discrete computer chip. The main 910, 1008 and L2 cache 904, 1002 memories are implemented individually and externally to the CPU 902, 1004. While the main memory 910, 1008 stores all of the data used by the CPU 902, 1004, the L2 cache 904, 1002 only stores a copy of recently used processor data. The L2 cache 904, 1002 is significantly smaller than the main memory 910, 1008, and as a result, can be accessed significantly faster.
To allow interfacing between the CPU 902, 1004, main memory 910, 1008 and L2 cache 904, 1002, a data bus 912 or buses 1010-1014 must exist between the CPU 902, 1004 and main memory 910, 1008, and between the CPU 902, 1004 and L2 cache 904, 1002. These buses 912, 1010-1014 are typically fairly wide (a width of 128 bits being quite common). Due to the IC packaging limitations discussed above, dedicating 128 IC pins for connecting these buses to the integrated circuit package comprising the CPU 902, 1004 may be impractical, or possibly just not within budget.
If the main memory and L2 cache buses could be shared, a significant reduction in IC pin count would result. However, two problems exist. First, the main memory data bus 912, 1012-1014 is typically heavily loaded (one to sixteen loads per line is common). The drivers of an L2 cache 904, 1002 are simply unable to drive this heavy of a load while maintaining their high speed accessibility.
Second, the decreasing geometries of CPUs and cache memories have resulted not only in smaller devices, but in devices with more limited voltage tolerances (voltage tolerance being a function of device geometry). Devices with smaller geometries are faster, and cheaper to make. However, their more limited voltage tolerance has often made the task of interfacing new and old devices difficult. For example, on one hand, an older, larger transistor found within a block of main memory might drive a logic high to 5.0 volts, whereas the smaller transistors of a newly manufactured cache might only drive a logic high to 3.3 volts (and be tolerable to receiving a maximum voltage of 3.3 volts). On the other hand, most all devices, new and old, will drive a logic low towards zero volts. A compatibility problem therefore exists at the high end of the voltage spectrum. If a high voltage device drives a line shared with a low voltage device in excess of the low voltage device's tolerance levels, the low voltage device can be seriously damaged.
In the past, components operating at various voltage levels have been connected to a common line or bus via a series of complex voltage translators (possibly contained within the buffer of FIG. 9). However, translators are costly, and typically impose a significant delay, thereby decreasing system performance.
It is therefore a primary object of this invention to provide methods and apparatus for isolating and/or translating voltage levels transmitted across a bus connecting a plurality of devices external to an IC package to a device internal to the IC package.
It is a further object of this invention to provide methods and apparatus which allow pins of an IC package to be shared among functional devices, thereby reducing an IC package's required pin count.
It is also an object of this invention to provide methods and apparatus which allow any plurality of devices to be connected to a common bus, regardless of the range of voltages used by each of the plurality of devices.